1. Field of the Invention
The invention relates to a display panel such as a liquid crystal display panel, an electroluminescence (abbreviated as EL) display panel or a plasma display panel.
2. Description of the Related Art
The display panel such as the liquid crystal display panel, EL display panel or plasma display panel forms a display pattern on a screen by selecting display pixels that are arranged like a matrix on an insulating substrate. Here, the system for selecting the display pixels can be represented by, for example, an active matrix drive system.
The active matrix drive system is the one in which the individual pixel elements are arranged as independent electrodes, the switching elements are connected to the individual pixel electrodes, and the pixel electrodes are selected by the switching elements to drive the display. The active matrix drive system is capable of producing a display maintaining excellent contrast and response, and can be used for the liquid crystal display panel or the like panel that features a reduced thickness and a small electric power consumption.
Concerning the display panels such as the liquid crystal display panel and the like, further, their has been developed and widely put into practical use the chip-on-glass (abbreviated as COG) mounting system in which a driver IC (integrated circuit) is directly mounted on a substrate of a glass or the like in order to drive the switching elements such as thin-film transistors (abbreviated as TFTs) arranged on the glass substrate.
The conventional display panel is constituted by a liquid crystal display device including a gate electrode wiring, a source electrode wiring, an input lead wiring and external connection terminals, and by a gate-driving IC, a source-driving IC and a flexible printed circuit (abbreviated as FPC) board.
The liquid crystal display device is constituted by an insulating substrate and an opposing substrate arranged at a position facing the insulating substrate. A liquid crystal layer is sealed between the insulating substrate and the opposing substrate, and a display region is formed on the insulating substrate.
Drive wiring regions are formed surrounding the display region on the insulating substrate. On the drive wiring regions are formed by COG method a gate driver and a source driver which are the driver ICs for driving liquid crystals. Gate electrode wirings and source electrode wiring drawn from the display region are connected in a plural number to the output sides of the gate driver and the source driver.
A plurality of input lead wirings and external connection terminals continuous to the input lead wirings are formed in predetermined patterns on the input sides of the gate driver and the source driver, and are electrically connected to the gate driver and to the source driver. Further, an FPC board is connected to the external connection terminals.
The power source voltage and signals sent from the FPC board are input to the gate driver and to the source driver through the input lead wirings. Signals from the gate driver and the source driver are sent to the display region through the gate electrode wiring and the source electrode wiring which are output wirings thereby to drive the TFT elements which are switching elements provided in the liquid crystal display device to display a desired image.
When it is attempted to increase the area and to improve the resolution of the above flat panel display (FPD), parasitic capacitance increases between the elements and the wiring and between the elements and the grounding electrodes to adversely affect the elements and circuit characteristics. Or, the resistance of the electrode wiring so increases that the drive signals are delayed to a large extent.
In order to operate the TFT elements on the display panel such as liquid crystal display panel, therefore, accent and delay of the signals are suppressed for the gate electrode wiring, source electrode wiring and input lead wiring connecting the pixel electrode to the drive power source in order to prevent erroneous operation caused by a drop in the voltage.
Due to limitation such as reduction in the outer size, further, the drive wiring region tends to become narrow, and it is becoming more important to decrease the resistance of the input lead wiring.
As for a conventional display panel, Japanese Unexamined Patent Publication JP-A 2000-19554 (2000) discloses “A COG-Type Liquid Crystal Display Element”. The structure of the input lead wiring and the procedure of production disclosed in JP-A 2000-19554 will now be described with reference to FIGS. 8 and 9.
FIGS. 8 and 9 are sectional views illustrating the structure of an input lead wiring in the conventional display panel, wherein FIG. 8 is a sectional view as viewed from a section in parallel with the direction of the current and FIG. 9 is a sectional view as viewed from a section perpendicular to the direction of the current.
First, a glass substrate is used as the insulating substrate 1, and a thin tantalum film is formed on the insulating substrate 1 by sputtering. Thereafter, an electrode wiring 2 of a first layer which is the lowermost layer of the input lead wiring is formed by patterning relying upon the photolithography technology.
Next, an SiNx film is formed as a gate-insulating film 3 in a desired pattern. On the gate-insulating film 3, there are formed an electrode wiring 4 of a second layer which is the electrode wiring of an indium tin oxide (ITO) and an electrode wiring 5 of a third layer which is a thin tantalum electrode wiring in predetermined patterns. Here, the electrode wirings are laminated to decrease the resistance of the input lead wiring.
Here, however, the thin tantalum film of the electrode wiring 2 of the first layer from which the gate-insulating film 3 has been partly removed, the thin tantalum film of the electrode wiring layer 5 of the third layer and the ITO film of the electrode wiring 4 of the second layer, are poorly adhering together and tend to be easily peeled off. The peeling of the films is due to a relationship between the thin tantalum film and the ITO film. That is, the thin tantalum film has a property of easily absorbing oxygen of the ITO film and tends to swell when it has once absorbed oxygen. Besides, when a thin tantalum film is formed on the ITO film, the ITO film becomes subject to be affected by the film stress from the thin tantalum film. This accounts for poor adhesion between the thin tantalum film and the ITO film, causing the films to be peeled off.
In order to decrease the peeling of film, it has heretofore been attempted as shown in FIG. 8 to limit the lengths of the electrically contacting portions C and D where the electrode wiring 2 of the first layer, the electrode wiring 4 of the second layer and the electrode wiring 5 of the third layer come into electric contact to be 100 μm or less in order to suppress the effect of film stress of the thin tantalum film upon the ITO film.
The input lead wirings other than those of the electrically contacting portions C and D are laminated one upon the other via the gate-insulating film 3 which adheres relatively favorably to the ITO film.
Referring next to FIG. 8, after the electrode wiring 5 of the third layer is formed, an insulating protection film 6 such as an SiNx film is formed except a connection portion P1 where the input lead wiring is connected to a connection pad 26 on the FPC side and a connection portion P2 where the input lead wiring is connected to a connection pad 27 on the side of the gate driver IC (hereinafter referred to as connection pad on the gate driver side).
After the insulating protection film 6 is formed, the input lead wiring, the connection pad 26 on the FPC side formed on the FPC board 25 and the connection pad 27 on the gate driver side formed on the gate driver 16, are connected together by being thermally press-adhered together by using an anisotropic conductive film (ACF) 28 which is obtained by mixing electrically conducting particles in a thermosetting resin film. Here, the regions E and F covered with the ACF 28 in the vicinities of the FPC board 25 and the gate driver 16 are about 0.2 mm to about 1.5 mm, and the input lead wirings are covered with the insulating protection film 6 in the regions other than the covering regions E and F.
The conventional input lead wiring is such that the electrode wiring 4 of the second layer which is the ITO electrode wiring is laminated on the electrode wiring 2 of the first layer via the gate-insulating film 3 which adheres relatively favorably to the ITO film. Further, the input lead wiring in the conventional display panel is such that various electrode wirings are laminated one upon the other to decrease the resistance of the input lead wiring and to prevent an increase in the wiring resistance.
In a flat portion E1 of the input lead wiring 21, further, the width W of the flat portion E1 of the input lead wiring shown in FIG. 9 is selected to be slightly as large as about 0.3 mm to about 1.5 mm to prevent an increase in the resistance of the input lead wiring. However, the flat portion E1 of the input lead wiring shown in FIG. 9 is accompanied by a problem in that the films tend to be peeled off. Besides, the edge portion F1 of the input lead wiring is accompanied by a problem of poor step coverage with the insulating protection film 6.
FIG. 10 is a sectional view illustrating the flat portion E1 of the input lead wiring in the conventional display panel.
In the flat portion E1 of the input lead wiring, the film peels in the interface between the gate-insulating film 3 and the electrode wiring 4 of the second layer designated at G in FIG. 10 and in the interface between the electrode wiring 4 of the second layer and the electrode wiring 5 of the third layer designated at H in FIG. 10.
The peeling of film at the portions G and H shown in FIG. 10 is due to a decrease in the adhesion of the films caused by the stress in the thin tantalum film of when the electrode wiring 5 of the third layer is being formed, caused by the contamination of the underlying film and by the process after the electrode wiring 5 of the third layer is formed, e.g., by the thermal stress that generates when the input lead wiring is connected to the connection pad 26 of the FPC side and the connection pad 27 of the gate driver side by the thermal press adhesion by using the ACF 28.
FIGS. 11A and 11B are sectional views illustrating an edge portion F of the input lead wiring in the conventional display panel.
Referring to FIG. 11A, the edge portion of the electrode wiring 2 of the first layer formed of the thin tantalum film is tapered so as to be favorably covered with the gate-insulating film 3. Here, the tapered shape is such that the thickness of the electrode wiring 2 gradually decreases toward the outer side (toward the left on the surface of the paper in FIGS. 11A and 11B), and that the upper surface of the electrode wiring 2 is inclined with respect to the surface of the insulating substrate 1, the angle θ subtended by the inclined surface and by the surface of the insulating substrate 1 being from 30° to 45° and the tapered length T being from 0.4 μm to 0.8 μm. Further, the electrode wiring 4 of the second layer and the electrode wiring 5 of the third layer are arranged on the electrode wiring 2 of the first layer via the gate-insulating film 3 so as to be overlapped on the edge portion of the electrode wiring 2 of the first layer. Therefore, the edge portions of the electrode wiring 4 of the second layer and of the electrode wiring 5 of the third layer are inversely tapered, and are poorly covered with the insulating protection film 6 positioned at an upper part of the electrode wiring 5 of the third layer. The inversely tapered shape stands for a shape in which the angle θ2 between the inclined surfaces S at the edge portions of the electrode wirings 4, 5 and the parallel surface of the insulating substrate 1 is not smaller than 90° in FIGS. 11A and 11B.
Herein, the step coverage stands for covering rugged portions of the underlying surface with the film in the step of forming the thin film on the surface of the substrate, and is also called step covering performance. When the step coverage becomes poor, the film poorly adheres and is peeled off.
The step coverage can be accomplished by increasing the thickness of the insulating protection film 6 resulting, however, in a decrease in the processing ability and an increase in the cost. By taking the processing ability and cost into consideration, therefore, the thickness of the insulating protection film 6 is selected to be 330 nm which is an optimum film thickness derived through experiment.
When a current-flowing test is conducted in an environment of a high temperature and a high humidity, e.g., a temperature of 50° C. and a relative humidity of 95% in a state of a poor step coverage, the insulating protection film 6 at the edge portion M is cracked as shown in FIG. 11A, and the electrode wiring 4x of the second layer which is the ITO electrode wiring is electrically corroded being affected by the humidity and electric current. Here, the electric corrosion stands for a phenomenon wherein when electrically conducting metals of different kinds are brought in contact with each other, the metal having a larger ionization tendency is corroded.
When the ITO electrode wiring 4x is split off due to electric corrosion, the electrode wiring 5 of the third layer and the insulating protection film 6 positioned thereon become an electrically conducting peeled piece N as shown in FIG. 11B. Being affected by the electric corrosion, the neighboring input lead wiring that is similarly peeled off and the electrically conducting peeled piece N cause a current to leak between the electrodes giving rise to the occurrence of erroneous operation.